1. Field of Invention
The present invention relates to a method of fabricating a semiconductor memory cell and particularly to a method for forming a polysilicon cylindrical capacitor in a stacked DRAM cell.
2. Description of Prior Art
A dynamic random access memory (DRAM) cell is a semiconductor memory device with one transistor and one capacitor, in which a data of one-bit can be stored in the capacitor by the charge stored therein. As the density of DRAM cells increases, the area occupied by the one memory cell decreases. Therefore, the present invention is devoted to the manufacture of a capacitor with a maximum capacity in a limited area with a minimum number of etch steps.
Semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs).
Current capacitor process are complicated, costly, and produce less than optimal rough polysilicon surfaces. For example, a conventional process for etching back dielectric and conductive layers over a cylinder capacitor electrode entail separate etch steps for etch type of layer etched and pre-cleans between each etch step. Moreover, current etch processes do not maintain good control over cylinder heights. The conventional processes require that the wafers be moved from one etcher (e.g., SiO.sub.2 etcher) to a wet pre-clean station and then to another etcher (e.g., PolySi etcher). This added cost and slows down the manufacturing process.
The prior art process degrades the performance (oxide/nitride/oxide (ONO) layer breakdown voltage) of the dielectric (ONO) layer because they produce a rough silicon surface. Typical polysilicon etches generate rough polysilicon surfaces. Rough polysilicon will create an antenna like surface which may result in a low ONO breakdown voltage. The conventional process needs special treatment to smooth the polysilicon surface or increase the ONO thickness to maintain the required breakdown voltage. However, a thicker ONO layer lowers capacitance.
Practitioners have tried to solve the problems of polysilicon cylinder fabrication. U.S. Pat. No. 5,219,780 (Jun) and U.S. Pat. No. 5,449,636 (Park) use 3 step processes to form a cylindrical capacitor. However, these processes can be further improved.